Devices and methods consistent with the present invention relate to a DMOS (Double Diffused Metal Oxide Semiconductor) type semiconductor device and a method for manufacturing the same.
As shown in FIG. 9, In a DMOS type semiconductor device (hereinafter abbreviated as “DMOS”) 100, an ion implantation opening 103 is formed in an isolation oxide layer 102 formed on a surface of a semiconductor layer (epitaxial growth layer) 101. In addition, in the DMOS 100, a body layer 104 is formed by implanting (doping) ions of an impurity element of a first conduction type from the ion implantation opening 103 and a source layer 105 and a back gate layer 106 are formed by implanting ions of an impurity element of a second conduction type opposite to the first conduction type using the same ion implantation opening 103. The DMOS 100 has an effect of achieving a short channel with ease and achieving high voltage resistance by a shape of the body layer 104 as a difference in a surface portion between diffusion depth of the body layer 104 and diffusion depth of the source layer 105 is configured as a channel length c, as shown in FIG. 11.
A conventional method for manufacturing the DMOS 100 is generally to form an n-type buried diffusion layer 108 by diffusing impurity ions into a p-type silicon substrate 107 through implantation of ions from a main surface of the silicon substrate 107 and form an n-type epitaxial growth layer 101 on the buried diffusion layer 108 and the main surface of the silicon substrate 107. This manufacturing method forms a relatively thick isolation oxide layer 102 on the epitaxial growth layer 101 using, for example, a LOCOS (Local Oxidation of Silicon) method. At this time, the ion implantation opening 103 is formed.
This manufacturing method forms a gate 110 on the epitaxial growth layer 101 through a gate oxide film 109 (see FIG. 10). This manufacturing method diffusively forms the body layer 104 in the epitaxial growth layer 101 by implanting ions of a p-type impurity element into the epitaxial growth layer 101 in self-alignment of some of the gate 110 in conjunction with the ion implantation opening 103. This manufacturing method diffusively forms a thin source layer 105 in the body layer 104 by implanting ions of an n-type impurity element into the body layer 104 in self-alignment of some of the gate 110 (see FIG. 11). This manufacturing method diffusively forms the back gate layer 106 in the body layer 104 by implanting ions of a p-type impurity element from the ion implantation opening 103 into the body layer 104.
This manufacturing method diffusively forms a drift layer 113 in the epitaxial growth layer 101 by implanting ions of an n-type impurity element into the epitaxial growth layer 101 at the same time of forming the above-mentioned source layer 105 or through a separate process, and additionally diffusively forms a drain layer 114 in the drift layer 113 by implanting ions of an n-type impurity element into the drift layer 113. In addition, this manufacturing method manufactures the DMOS 100 by carrying out an electrode forming process and the like, as shown in FIG. 9.
Patent Document 1 discloses an N channel type high voltage resistant transistor of a DMOS type with improved voltage resistance between a source and a drain in a state where the transistor is turned on and channel current flows through the transistor. The high voltage resistant transistor has a body layer including a first body layer formed to include a channel region between a source layer and a drain layer and a second thin body layer projecting from the first body layer toward a region under the drain layer, for the purpose of improvement of a voltage resistance characteristic by alleviating an electric field by a drain voltage in the body layer.
Patent Document 1: Japanese Patent Publication No. 2004-39774 A
In the DMOS 100, an annealing treatment (thermal oxidation treatment) is carried out while the source layer 105 and the back gate layer 106 are being formed after the body layer 104 is formed. In the DMOS 100, while the gate 110 is formed on the gate oxide film 109, the gate oxide film 109 at an end of the gate 110 is affected by the thermal oxidation treatment carried out in the above-mentioned post-process, thereby producing a gate bird's beak 115 unstable in its thickness or shape as shown in FIG. 11.
In the DMOS 100, as described above, the source layer 105 is diffusively formed in the body layer 104 by implanting ions of an impurity element from the ion implantation opening 103 into the body layer 104. In the DMOS 100, although the ions of the impurity element is implanted in self-alignment of an end of the gate 110 at that time, diffusion of the ions from the end of the gate 110 into a region under the end of the gate 110 is small. On this account, in the DMOS 100, the source layer 105 is formed in the body layer 104 over a region in which the above-mentioned gate bird's beak 115 is produced.
In the DMOS 100, as described above, the difference in the surface portion between the diffusion depth of the body layer 104 and the diffusion depth of the source layer 105 is configured as the channel length C. In the DMOS 100, since the source layer 105 is formed over the region in which the gate bird's beak 115 is formed, the source layer 105 is affected by irregularity of the thickness and shape of the gate bird's beak 115, which results in an irregular characteristic of the semiconductor 100 and a low yield thereof.